Solar cells are photovoltaic devices that convert sunlight directly into electrical power. The most common solar cell material is silicon, which is in the form of single or polycrystalline wafers. However, the cost of electricity generated using silicon-based solar cells is higher than the cost of electricity generated by the more traditional methods. Therefore, since early 1970's there has been an effort to reduce cost of solar cells for terrestrial use. One way of reducing the cost of solar cells is to develop low-cost thin film growth techniques that can deposit solar-cell-quality absorber materials on large area substrates and to fabricate these devices using high-throughput, low-cost methods.
Group IBIIIAVIA compound semiconductors that contain Group IB (Cu, Ag, Au), Group IIIA (B, Al, Ga, In, Tl) and Group VIA (O, S, Se, Te, Po) materials or elements of the periodic table are excellent absorber materials for thin film solar cell structures. Especially, compounds of Cu, In, Ga, Se and S which are generally referred to as CIGS(S), or Cu(In,Ga)(S,Se)2 or CuIn1-xGax (SySe1-y)k, where 0≦x≦1, 0≦y≦1 and k is approximately 2, have already been employed in solar cell structures that yielded conversion efficiencies approaching 20%. Absorbers containing Group IIIA element Al and/or Group VIA element Te also showed promise. Therefore, in summary, compounds containing: i) Cu from Group IB, ii) at least one of In, Ga, and Al from Group IIIA, and iii) at least one of S, Se, and Te from Group VIA, are of great interest for solar cell applications. It should be noted that although the chemical formula for CIGS(S) is often written as Cu(In,Ga)(S,Se)2, a more accurate formula for the compound is Cu(In,Ga)(S,Se)k, where k is typically close to 2 but may not be exactly 2. For simplicity we will continue to use the value of k as 2. It should be further noted that the notation “Cu(X,Y)” in the chemical formula means all chemical compositions of X and Y from (X=0% and Y=100%) to (X=100% and Y=0%). For example, Cu(In,Ga) means all compositions from CuIn to CuGa. Similarly, Cu(In,Ga)(S,Se)2 means the whole family of compounds with Ga/(Ga+In) molar ratio varying from 0 to 1, and Se/(Se+S) molar ratio varying from 0 to 1.
The structure of a conventional Group IBIIIAVIA compound photovoltaic cell such as a Cu(In,Ga,Al)(S,Se,Te)2 thin film solar cell is shown in FIG. 1. The device 10 is fabricated on a substrate 11, such as a sheet of glass, a sheet of metal, an insulating foil or web, or a conductive foil or web. The absorber film 12, which comprises a material in the family of Cu(In,Ga,Al)(S,Se,Te)2, is grown over a conductive layer 13 or contact layer, which is previously deposited on the substrate 11 and which acts as the electrical contact to the device. The substrate 11 and the conductive layer 13 form a base 13A on which the absorber film 12 is formed. Various conductive layers that include Mo, Ta, W, Ti, and their nitrides etc. have been used in the solar cell structure of FIG. 1. If the substrate itself is a properly selected conductive material, it is possible not to use the conductive layer 13, since the substrate 11 may then be used as the ohmic contact to the device. After the absorber film 12 is grown, a transparent layer 14 such as a CdS, ZnO, CdS/ZnO or CdS/ZnO/ITO etc. stack is formed on the absorber film 12. Radiation 15 enters the device through the transparent layer 14. Metallic grids (not shown) may also be deposited over the transparent layer 14 to reduce the effective series resistance of the device. The preferred electrical type of the absorber film 12 is p-type, and the preferred electrical type of the transparent layer 14 is n-type. However, an n-type absorber and a p-type window layer can also be utilized. The preferred device structure of FIG. 1 is called a “substrate-type” structure. A “superstrate-type” structure can also be constructed by depositing a transparent conductive layer on a transparent superstrate such as glass or transparent polymeric foil, and then depositing the Cu(In,Ga,Al)(S,Se,Te)2 absorber film, and finally forming an ohmic contact to the device by a conductive layer. In this superstrate structure light enters the device from the transparent superstrate side. A variety of materials, deposited by a variety of methods, can be used to provide the various layers of the device shown in FIG. 1.
In a thin film solar cell employing a Group IBIIIAVIA compound absorber, the cell efficiency is a strong function of the molar ratio of IB/IIIA. If there are more than one Group IIIA materials in the composition, the relative amounts or molar ratios of these IIIA elements also affect the properties. For a Cu(In,Ga)(S,Se)2 absorber layer, for example, the efficiency of the device is a function of the molar ratio of Cu/(In+Ga). Furthermore, some of the important parameters of the cell, such as its open circuit voltage, short circuit current and fill factor vary with the molar ratio of the IIIA elements, i.e. the Ga/(Ga+In) molar ratio. In general, for good device performance Cu/(In+Ga) molar ratio is kept at around or below 1.0. As the Ga/(Ga+In) molar ratio increases, on the other hand, the optical bandgap of the absorber layer increases and therefore the open circuit voltage of the solar cell increases while the short circuit current typically may decrease. So far experimental results have shown that a Ga/(Ga+In) ratio of about 0.2-0.3 at the junction area (top 0-1 to 0.3 μm of the CIGS surface) yields the highest efficiency solar cells. When this ratio increases further, the device efficiency gets reduced. Although the reasons for this are not fully understood, it is reported that the electronic quality of CIGS material gets worse as the Ga/(Ga+In) ratio increases beyond 0.3. It is important for a thin film deposition process to have the capability of controlling both the molar ratio of IB/IIIA, and the molar ratios of the Group IIIA components in the composition.
One attractive technique for growing Cu(In,Ga)(S,Se)2 or CIGS(S) type compound thin films for solar cell applications is a two-stage process where metallic components of the Cu(In,Ga)(S,Se)2 material are first deposited onto a substrate during the first stage of the process, and then reacted with S and/or Se in a high temperature annealing process during the second stage. Sputtering and evaporation techniques have been used in prior art approaches to deposit the layers containing the Group IB and Group IIIA components of the precursor stacks during the first stage of such a process. In the case of CuInSe2 growth, for example, Cu and In layers were sequentially sputter-deposited on a substrate and then the stacked film was heated in the presence of gas containing Se at elevated temperature for times typically longer than about 30 minutes, as described in U.S. Pat. No. 4,798,660. More recently U.S. Pat. No. 6,048,442 disclosed a method of sputter-depositing a stacked precursor film that includes a Cu—Ga alloy layer and an In layer to form a Cu—Ga/In stack on a metallic back electrode layer and then reacting this precursor stack film with one of Se and S to form the absorber layer. U.S. Pat. No. 6,092,669 described sputtering-based equipment for producing such absorber layers. According to a method described in U.S. Pat. No. 4,581,108, a Cu layer is first electrodeposited on a substrate; this is then followed by electrodeposition of an In layer and heating of the deposited Cu/In stack in a reactive atmosphere containing Se to form CuInSe2 or CIS.
Heating of metallic precursors to form CIS or CIGS(S) type layers may be carried out in various ways. Some groups use standard furnace processing to heat the layers slowly (such as at a rate of 1° C./second) to the reaction temperature of 400-500° C. in presence of Se and/or S. This furnace type processes generally use a gas as the source of Group VIA material. For example, H2Se and H2S are commonly used to react precursors that include Cu and In, to form CIS layers. The reaction time in such a process is usually in the range of 0.5-2 hours. For precursors that also contain a Group VIA material (such as a base/Cu/In/Se stack) a rapid thermal processing (RTP) process with a temperature rise rate of at least 10° C./second is preferred as the temperature passes through the melting point of Se (about 220° C.), because reportedly such a high rise rate of temperature around the Se melting point avoids the formation of defects on the surface of the film which may result from de-wetting of the surface by the molten Se if too much time is allowed for Se to melt and form “balls” on the surface due to surface tension. Such defects are known to yield inhomogeneous film morphology, poor adhesion of the CIS layer and low solar cell efficiency. It is stated that such problems may be avoided by passing through the critical temperature range between 80° C. and 300° C. at a temperature rise rate of about 10° C./sec by using RTP (see for example, F. Karg et al., Proceedings of IEEE Photovoltaic Specialists Conf. 1993, page:441). High rate RTP has been used by others also to form CIS layers (see for example, A. Gabor et al., AIP Conference Proceedings 268, 1992, page. 236, and G. Mooney et al., Solar Cells, vol: 30, page:69, 1991). Although various rise rates for temperature were evaluated in these early studies a rate of around 10° C./second was found to be best in terms of morphology of the resulting CIS films. In these early studies Ga was not added to the absorber to form CIGS.
Although CIS formation using two-stage processes employing slow annealing using a gaseous Se source or fast annealing using a Se layer deposited on a Cu/In precursor is rather straight forward, complications arise when Ga is added to the precursor to form a CIGS absorber. Curve A in FIG. 2 schematically shows a typical distribution profile for the Ga/(Ga+In) molar ratio for a Cu(In,Ga)Se2 absorber layer formed by a two-stage process involving selenization of metallic precursors including Cu, In and Ga. As can be seen from this figure, one problem faced with the selenization type processes or two-stage processes to grow CIGS is the difficulty of distributing Ga uniformly through the thickness of the absorber layer formed after the reaction of the Cu, In and Ga containing metallic precursor film with Se. It is believed that when a metallic precursor film including Cu, In and Ga is deposited first on a contact layer (such as Mo) of a base and then reacted with Se, the Ga-rich phases segregate to the film/base interface (or the film/contact layer interface) because reactions between Ga-bearing species and Se are slower than the reactions between In-bearing species and Se. Therefore, such a process yields compound absorber layers with surfaces that are rich in In and poor in Ga. Various reports in the literature have described this phenomenon (see for example, Basol et al., Progress in Photovoltaics, vol. 8 (2000) p. 227, Alberts et al., Solar Energy Materials and Solar Cells, vol. 64 (2000) p. 371, Marudachalam et al., J. Appl Phys., vol. 82 (1997) p. 2896, Delsol et al., Solar Energy Materials and Solar Cells, vol. 82 (2004) p. 587). Furthermore, such Ga grading is observed even when a RTP process is used to react precursor layers including Cu, In, Ga and Se (see for example, J. Palm et al., MRS Proceedings vol: 763, page B6.8.1, 2003). It is for this reason that, as can be seen in some of the references cited above, increasing the bandgap value of the absorber near its surface region is usually achieved by first obtaining a CIGS layer with a Ga poor surface (such as shown in FIG. 2 Curve A) and then reacting this layer with sulfur (S) at high temperature so that the Ga-poor, In-rich surface layer is converted into a high bandgap sulfide material as shown by the S profile curve B in FIG. 2. In this case the absorber layer is a CIGS(S) layer containing both S and Se.
When a solar cell is fabricated on an absorber layer with Ga gradation such as the one shown in FIG. 2, Curve A, the active junction of the device is formed within the absorber surface region with a low Ga/(Ga+In) ratio, which is near-zero for Curve A. This surface portion or region, therefore, is practically a CIS or CuInSe2 layer with a small bandgap and consequently solar cells fabricated on such layers display low open circuit voltages (typically in the range of 400-500 mV) and thus lower efficiencies. It should be noted that the bandgap values for CuInSe2 and CuGaSe, are around 1.0 eV and 1.7 eV, respectively and by adjusting the amount of Ga in CIGS, the bandgap may be tuned to any value between these two values. Relatively uniform Ga distribution through a CIGS layer may be readily obtained by a technique such as co-evaporation. Solar cells fabricated on such absorbers display higher voltage values of typically over 600 mV due to the presence of Ga (typically 20-30%) near the surface region. The world-record-holding CIGS solar cell with over 19% conversion efficiency was demonstrated on such an absorber obtained by a co-evaporation process (see, for example Ramanathan et al., Progress in Photovoltaics, vol. 11 (2003) p. 225). Obtaining Ga distribution profiles with more Ga near the surface region for absorbers formed by low cost two-stage processes is important to increase the performance of such absorbers. Several attempts were made to investigate the possibility of controlling Ga distribution within absorbers grown by the two-stage processes. Marudachalam et al. (J. Appl. Phys., vol. 82 (1997) p. 2896), for example, annealed the already formed CIGS layers at high temperatures to diffuse Ga to the surface from the back side of the absorber. Nakagawa et al. (14th European Photovoltaic Solar Energy Conf., 1997, p. 1216) prepared CIGS layers using various precursor stacks of In—Se/Cu/Ga—Se, In—Se/Ga—Se/Cu, Cu/In—Se/Ga—Se, Cu/Ga—Se/In—Se, Ga—Se/Cu/In—Se, Ga—Se/In—Se/Cu, In—Se/Ga—Se/Cu/Ga—Se, Ga—Se/In—Se/Cu/Ga—Se, and Ga—Se/In—Se/Ga—Se/Cu. As can be seen from this list, the prior art attempts used precursor stacks including compounds or selenides such as gallium selenide (Ga—Se) and indium selenide (In—Se) in attempts to distribute Ga in various ways in the stack. These indium selenide and gallium selenide phases are phases with high melting temperatures of above 600° C. CIGS formation by two-stage process takes place at temperatures below 600° C., typically at around 450-575° C. Therefore, metallic precursors having low temperature melting phases (such as In and Ga metals and metallic alloys such as In—Ga, Cu—Ca, Cu—In and Cu—In—Ga), with melting points below 600° C., may be preferred since they may facilitate liquid phase assisted growth which yields large grain growth.
As the brief discussion above demonstrates there is still a need to develop a two-stage approach that can utilize precursor layers substantially including metallic ingredients and still provide CIGS absorber layers with a Ga/(Ga+In) molar ratio in the range of 0.1-0.3 near its surface region, i.e. within the top 0.1-0.3 um of the absorber layer.